The present invention relates in general to phase locked oscillators and, more particularly, to a digital controlled oscillator that is phase locked to an input reference clock signal.
A conventional phase lock loop (PLL) generally includes a phase detector for monitoring a phase difference between an input signal and an output signal of a voltage controlled oscillator (VCO). The phase detector generates an up control signal and a down control signal for a charge pump to charge and discharge a loop filter at a loop node at the input of the VCO. The loop voltage developed across the loop filter determines the output frequency of the VCO. The up and down control signals driving the charge pump set the proper loop filter voltage at the input of the VCO to maintain a predetermined phase relationship between the signals applied to the phase detector, as is well understood.
PLLs are widely used in data communications, local area networks in computer applications, microprocessors and data storage applications to control data transfers. The PLL provides a clock signal operating in phase with respect to the input reference signal that clock the various registers and logic gates used in the data transfer. PLLs are generally analog in nature and as such are subject to glitches in power supply potential that can cause the loop to lose phase lock. The switching of output buffers commonly used in digital design are known to glitch the power supply lines. The power supply glitches alter loop node voltage and drive the VCO to radically different frequencies. The PLL must search and reacquire phase lock. Another problem with conventional PLLs is the VCO's sensitivity to temperature variation. As the temperature varies, so does the VCO output frequency.
Hence, a need exists to provide an oscillator clock signal phase locked to an input reference signal that is robust to power supply and temperature variation.